FPGA implementation • summer hack
a fun summer project from a few years back: Grissess, a close friend, and i came up with some simple constraints for an ISA and then implemented it in HDL (Chisel/SpinalHDL/MyHDL). github.com/emberian/absass
the project
we designed a simple RISC instruction set architecture and implemented emulators, compilers, and FPGA simulations with hardware description languages. the goal was to see how minimal we could make it while still being useful, and to explore the hardware/software boundary.
the implementation was surprisingly efficient: i was able to retire one instruction per clock cycle at the maximum FPGA rate. on lucky runs of yosys (the synthesis tool), we hit 240MHz—single-cycle retirement at that frequency was deeply satisfying.
why this was fun
this project was pure joy. no formal methods, no proofs, no production concerns—just the pleasure of:
- designing an ISA with clean, simple constraints
- implementing digital logic in HDL
- seeing it actually work on real hardware
- optimizing for clock speed and resource usage
- learning about FPGA synthesis and timing analysis
it's the kind of project that reminds you why you got into this field: the immediate feedback loop of hardware design, the satisfaction of seeing something you designed actually execute instructions at hundreds of millions of cycles per second.
hardware/software co-design
implementing an ISA in hardware gives you deep appreciation for the hardware/software interface. every instruction you add has area and timing costs. every addressing mode adds muxes and control logic. you start thinking about how compilers would target your ISA and what primitives would be genuinely useful versus just neat to have.
it's the inverse of systems programming: instead of working within the constraints the hardware gives you, you're defining what those constraints are. and then immediately feeling those constraints when your synthesis runs show timing violations or resource exhaustion.